Random Access Memory

random access memory

A type of computer that can be accessed randomly; that is, any byte of memory can be accessed without touching the preceding bytes. 

Types of random access memory

• DRAM memories (Dynamic Random Access Module), which are inexpensive. They are used essentially for the computer's main memory.
• SRAM memories (Static Random Access Module), which are fast and costly. SRAM memories are used in particular for the processors cache memory.

 

Operation of the random access memory

 The random access memory comprises hundreds of thousands of small capacitors that store loads. When loaded, the logical state of the capacitor is equal to 1, otherwise it is 0, meaning that each capacitor represents one memory bit.
 

Given that the capacitors become discharged they must be constantly recharged (the exact term is refresh) at regular intervals, known as the refresh cycle. DRAM memories for example require refresh cycles of around 15 nanoseconds (ns). 

Each capacitor is coupled with a transistor (MOS-type) enabling "recovery" or amendment of the status of the capacitor. These transistors are arranged in the form of a table (matrix) thus we access a memory box (also called memory point) via a line and a column.  

Each memory point is thus characterised by an address which corresponds to a row number and a column number. This access is not instant and the access time period is known as latency time. Consequently, time required for access to data in the memory is equal to cycle time plus latency time.

Thus, for a DRAM memory, access time is 60 nanoseconds (35ns cycle time and 25ns latency time). On a computer, the cycle time corresponds to the opposite of the clock frequency; for example, for a computer with frequency of 200 MHz, cycle time is 5 ns (1/200*10⁶)).

Consequently a computer with high frequency using memories with access time much longer than the processor cycle time must perform wait states to access the memory. For a computer with frequency of 200 MHz using DRAM memories (and access time of 60ns), there are 11 wait states for a transfer cycle. The computer's performance decreases as the number of wait states increases, therefore we recommend the use of faster memories.